1. Field of the Invention
The present invention generally relates to the field of semiconductor devices and more particularly to an adaptively controlled, self-aligned, short channel semiconductor device and method for manufacturing the same.
2. Description of the Related Art
The trend in the semiconductor industry is to reduce the geometry of semiconductor devices to thereby increase the number of such devices available in a given area (increased density) of an integrated circuit (IC) chip. As the integration degree of semiconductor devices becomes higher, the device size must be reduced. The increased density of semiconductor devices in a given area of an IC chip results in an increased performance by the IC chip including faster operating speeds and lower power consumption necessary to supply the IC chip.
The size of a semiconductor device such as a transistor is in large part dependent on the length of the "channel" of the transistor, that is, a thin region of the device that supports conduction. A conventional semiconductor device known as a silicon gate metal oxide ("MOS") field effect transistor 5 (MOS transistor) depicting a channel region is shown in prior art FIG. 1. (In the attached figures, it should be understood that the thicknesses are not represented to scale and the cross-sections are exaggerated for clarity in the explanation of the invention). The MOS transistor is formed on a silicon wafer 10, typically a P-type wafer. The silicon wafer 10 is doped with an N-type impurity to form a source region 15 and drain region 20, with the distance between the source and drain regions defining the channel length 25 of the MOS transistor 5. Isolation oxide regions 30 isolate the MOS transistor 5 from other devices on the wafer. The gate structure 35 is composed of a polysilicon region 40 and a gate oxide 45. A deposited oxide layer 46 surrounds the gate structure 35, while conductive metal layers 50 are coupled to the source, drain and gate to couple the device to other devices on the IC.
Channel lengths, such as the channel length 25 of FIG. 1, are currently defined in the submicron region. State of the art devices currently have channel lengths ranging from approximately 0.18 .mu.m to 0.25 .mu.m. The trend discussed above to reduce the geometry of semiconductor devices has resulted in attempts to reduce the channel length of a semiconductor device to dimensions below 0.1 .mu.m and even down to 0.05 .mu.m. However, as the channel lengths of these devices are reduced, problems with the design, operation and fabrication of the devices occur. Features such as lightly doped-drain (LDD) extension regions, having a lower impurity concentration than the source and drain regions, solve some of the operational problems associated with short-channel devices but other problems, including that of the accuracy of equipment currently employed to fabricate devices, remain.
One such problem is the alignment of the source and drain regions of a semiconductor device around such a small channel length (down to 0.05 .mu.m). Prior art FIG. 1 shows that the source and drain regions meet the gate oxide region 45 of the gate region 35 at reference points 55 producing a shorter effective channel length of the device. When the device is formed, there is some overlap by the gate region over the source and drain regions. Generally, any such overlap becomes a region of unwanted capacitance. It is well known to employ self-alignment of the source and drain regions to the gate regions by forming the gate region first and then aligning the source and drain regions around the gate region. However, with ever smaller devices, processing limitations make such alignment more difficult
A further limitation on size reduction concerns photolithography equipment and techniques currently employed. Such equipment is limited in resolution and by physical factors such as reflection and resist mask chemistry.
In a standard, prior art process for forming a transistor such as that shown in FIG. 1, two masks are used to define the device. The first mask defines a window of silicon with an isolation oxide, while a second mask defines where the polysilicon gate will be located. Overlay errors (the error in the alignment of the polysilicon mask in respect to the isolation mask), can become significant once device dimensions become very small (such as, for example, a maximum error of 0.75 .mu.m on a 0.2 .mu.m length of diffusion area EPROM). Hence, in a worst case, source resistance would only be 45% of drain resistance, which is not an acceptable design feature of the device. Typical photoresist masks, when applied to reflective films such as polysilicon or silicon are difficult to accurately pattern due to the reflectivity of the films, making it difficult to control line widths and other critical dimensions. Subsequent etching of the underlying films such as polysilicon can introduce more variations. Hence, with channel lengths below 0.1 .mu.m, there remain several difficult manufacturing problems.
In U.S. Pat. No. 5,571,738 invented by Zoran Krivokapic issuing Nov. 5, 1996 (Krivokapic), the channel length of a transistor is controlled by varying the thickness of an insulation spacer layer. Krivokapic discloses one technique for using insulation layers to define the effective channel length in the range of 0.35 .mu.m by varying the insulation layer from about 300 to 1,000 .ANG.. Krivokapic teaches a method for forming a relatively conventional cross-section of a raised source/drain MOS transistor. There is a need for a semiconductor device and method for making the same device that ensures that, even at sub-0.1 .mu.m dimensions, there is very little overlap in the source/drain and gate.
Still another problem is the electrical interference between the close source, gate and drain contacts due to the short channel length. As the channel length 25 of FIG. 1 becomes shorter, it is clear that the metalization layers 50 will continue to move closer together and thereby cause electrical interference between the contacts. There is therefore a need to separate the drain, source and gate contacts to avoid electrical interference as the channel length is reduced.
A further problem is that non-planarized contacts of the source, drain and gate regions at the contact mask level result in an uneven topography that may cause excessive over etching of the silicide layer overlying the polysilicon. Increasing chip density has placed more components on the wafer surface, which in turn, has decreased the area available for surface wiring. The answer to this dilemma has been dual and triple level layer connection schemes, with numerous layers of dielectric and metal layers. Multilevel layer schemes are simple in concept but present one of the semiconductor technology's biggest challenges of forming a planarized device. A device with a multi-level layer design will be dense and have a number of etched surface layer, leaving a topology of different step heights and a mix of surfaces. The type of surface requires planarization techniques to minimize thinning of deposited conduction layers over the steps and allow precise imaging. A need therefore exists to have a fully planarized device at the contact mask level to make the device more reliable.
A still further problem is the cost of purchasing new equipment capable of manufacturing devices with such short channel lengths. To accomplish the move to smaller geometries at a relatively feasible cost, the same equipment used in the fabrication of the devices used to manufacture 0.25 .mu.m must be reusable at these geometries down to 0.05 .mu.m.
The present invention is directed to overcoming one or more of the problems as set forth above.